As semiconductor device dimensions approach the sub-half-micron level, one of the limiting factors for further reduction in size is the area required for device interconnections. One solution has been multilevel metallization in which two or more interconnect layers are formed on top of a device, separated by a dielectric layer, and coupled by vias which are filled with a via metallization. Even with multilevel metallization, the reduced area required for vias restricts scaling of interconnect structures. Photolithography technology has advanced so that submicron via windows can be formed but due to contact resistance problems, it has not been possible to take advantage of these advances.
One of the major contributors to the increase in contact resistance is the formation of via veils during the via etching process. In a typical electrical interconnect formation process, a conductor, such as aluminum, is provided on a surface of the semiconductor substrate. An insulating layer is deposited on top of the conductor to cover it, and a photosensitive resist layer is masked on top of the insulating layer. An etchant is then used to pattern the photoresist layer etching through the insulative layer to expose an electrically conductive surface to enable electrical connection to the conductor level. However, during the etching process, the aluminum underlying substrate resputters to form an aluminum oxide that deposits on the sidewalls of the via. This phenomenon is known as a via veil, wherein the redeposition of the oxide causes a micromasking of the via to create a tapering of the via such that the bottom of the via is smaller than the top.
The contact resistance of the via metallization is inversely proportional to the cross-sectional area of the contact at a bottom and a top interface area between the via metallization and the interconnect layers. Effective via metallization must have sufficient contact area at both the bottom and top of the via to provide low resistance contact. However, the via veil formation, which causes a tapered via profile, results in the bottom contact area being smaller than the top contact area which increases contact resistance. In order to compensate, the size of the via must increase or the contact resistance increases. Increasing the size of the via is undesirable in the face of submicron technology because of design requirements and spacing of adjacent via structures. In general the via veil increases the resistance of the interconnect and lowers its conductance and is generally undesirable especially in ultra large scale integration (ULSI) devices.
Alternatively, an organic solvent can be used to remove the aluminum oxide residue along the sidewalls of the via to increase the bottom contact area. However, use of the solvent does not entirely eliminate the aluminum oxide veil. Moreover, the solvent often times attacks the underlying substrate as well as the aluminum oxide, thus causing isotropic undercut of the underlying metal resulting in poor step coverage of the deposited via glue layer. This undercut results in poor via resistance which can lead to reliability failures.
Another contact resistance problem attributable to via veils becomes apparent with unlanded vias. If the mask for the vias is not aligned perfectly with the underlying substrate, the resulting vias are not centered over the conductor layer but are partially unlanded off the conductor. Unlanded vias may contact the conductor layer in both the vertical and horizontal direction due to the alignment tolerance of current photolithographic tools causing the printing of features to be less than optimal such that the etching process partially or completely exposes the conductor in both horizontal and vertical directions. This situation is extremely detrimental when the profile of the via is non-vertical or tapered and size of the via profile is poorly controlled causing parasitic electrical resistance between two connected conductor layers. Poor via resistance has been found to be a major mode of failure for submicron semiconductor devices.
An additional problem encountered in the formation of multilevel interconnects is overetching. When the dielectric layer is etched to form vias, the etchant typically etches at a uniform rate through the material, but the contact depths for multilevel interconnects are necessarily different due to planarization in the underlying topography. Therefore, the conductor level that is closest to the top surface of the dielectric layer is exposed first, but the etching must continue until the other conductors are exposed to form the second level interconnect during which time the etchant continues to act upon the first conductor level. Thus, overetching becomes a problem as the thin first conductor level is undesirably removed during the extended etching causing variability in via size and veil formation.